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low power, 24-bit/16-bit sigma-delta adc with in-amp prelim inary technical data ad7798/AD7799 rev. prd. in fo rmation furn is h e d by an al o g dev i ces is believed to be a ccu rate and r e liable. how e ver, no r e spons i bili ty is assumed by analog devices fo r its use, nor f o r an y i n fri n geme nt s of p a t e nt s or ot her ri g h t s o f th ird parties th at may result fro m its use . specifications subject to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot he rwi s e un der a n y p a t e nt or p a t e nt r i ghts of anal og de vices. trad emarks an d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures resolution: ad77 98: 1 6 -bit ad77 99: 2 4 -bit three dif f erent i al ana l og inputs low noise programmable ga in amp rms noise: 80 nv (gain = 6 4 ) at 16.6 hz update rate (ad77 98) 65 nv (gain = 6 4 ) at 16.6 hz upd a te rate (ad 7 7 99) 30 n v (ga i n = 64) at 4 hz up date rat e (a d7 799) update rat e : 4 hz to 50 0 h z power supply: 2.7 v t o 5.25 v operation normal: 330 a typ ( ad7 798) 400 a typ (a d779 9) power-down: 1 a max simultaneous 50 hz/6 0 h z re jection two program m able d i gital ou tpu t s internal clock oscillator reference det e ct 100 na burnou t currents low side power switch independent i n terface power supply 16-lead tssop interf a c e 3-wire seri al spi?, qspi?, microwire?, an d dsp compatible schmitt trigger on sclk applic a t io ns pressure m eas urement weigh scales func ti on a l bl ock di a g r a m ad 77 9 9 / ad77 9 8 seria l inte rf a c e an d co nt r o l lo gic i n terna l cl ock si gma d e l t a ad c ain1(-) ain2(-) mux in-am p do u t / r d y di n sc l k cs dv dd av dd gn d re ferenc e det e ct gn d ain1(+ ) pwrsw ai n 2 ( + ) a i n 3 (-) /p 2 ai n 3 ( + ) / p 1 fi g u r e 1 . gener a l description the ad7798/AD7799 is a lo w p o w e r , co m p let e a n alog f r o n t end f o r l o w f r eq ue n c y m e a s ur em en t a p p l ica t i o n s . th e de v i ce co n t a i n s a lo w no is e 24-b i t (AD7799)/ 16-b i t (ad7798) -? ad c wi t h t h r e e dif f er en t i al in pu ts. th e o n -chi p lo w n o is e in st r u m e n t a t ion a m pl if ier m e an s t h a t sig n a l s of sma l l a m pli t ude can b e in ter f ace d dir e c t l y t o t h e a d c. w i t h a ga i n s e t t in g o f 64, the r m s n o is e is 8 0 nv f o r ad77 98 a nd 65 nv f o r th e AD7799 a t 1 6 .6 h z . t h e d e vice con t a i n s a lo w side p o w e r swi t ch w h ich is us ef u l in b r idge a p plic a t i o n s . the s w i t ch a l lo ws t h e b r id ge t o b e dis c o n n e c t e d f r o m t h e p o w e r su p p l y w h en con v ersio n s a r e n o t b e i n g p e r f o r m e d an d t h is w i l l mini mis e p o w e r co n s um p t ion. the device als o has 100 na b u r n o u t c u r r en ts. th es e c u r r en ts a r e us e d t o dete c t if s e n s o r s co nn e c te d t o t h e a n a l og in p u ts a r e b u r n t o u t. o t h e r o n -chi p fe a t ures in cl ude an in t e r n a l clo c k s o t h e us er do es no t ha v e t o s u p p ly a clo c k t o t h e de vice . this r e d u ces t h e com p on e n t co u n t in a sys t em an d p r o v ides b o a r d s p ace s a vin g s. the u p da t e r a t e is p r og ra mma b l e o n t h e ad7798/99. i t ca n be va r i ed f r o m 4 h z t o 500 h z . the p a r t o p era t es wi t h a si n g le p o w e r s u p p l y f r o m 2.7 v t o 5.2 5 v . i t co n s u m es a c u r r en t o f 380 ua maxim u m fo r th e ad7798 a nd 450 ua maxim u m f o r the AD7799. th e AD7799/ad7798 is h o us e d in a 16-l e ad t ssop p a cka g e.
ad7798/AD7799 preliminary technical data rev. prd. page 2 of 17 table of contents AD7799/ad7798specifications .................................................. 3 timing characteristics , .................................................................... 6 absolute maximum ratings ............................................................ 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 on-chip registers ........................................................................... 12 communications register (rs2, rs1, rs0 = 0, 0, 0) .............. 12 status register (rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x88) ............................................................................................. 13 mode register (rs2, rs1, rs0 = 0, 0, 1; power-on/reset = 0x000a) ........................................................................................ 13 configuration register (rs2, rs1, rs0 = 0, 1, 0; power- on/reset = 0x0710) .................................................................... 15 data register (rs2, rs1, rs0 = 0, 1, 1; power-on/reset = 0x0000 (ad7798)/ 0x000000 (AD7799)) ................................ 16 id register (rs2, rs1, rs0 = 1, 0, 0; power-on/reset = 0xx8 (ad7798)/ 0xx9 (AD7799)) ..................................................... 16 offset register (rs2, rs1, rs0 = 1, 1, 0; power-on/reset = 0x8000 (ad7798)/0x800000 (AD7799)) ................................. 17 fullscale register (rs2, rs1, rs0 = 1, 1, 1; power- on/reset = 0x5xxx (ad7798)/0x5xxx000 (AD7799)) ..... 17 typical application ........................................................ 17 revision history prelim d, june 2004: initial version
preliminary technical data ad7798/AD7799 rev. prd. page 3 of 17 AD7799/ad7798specifications 1 table 1. (av dd = 2.7 v to 5.25 v; dv dd = 2.7 v to 5.25 v; gnd = 0 v; refin(+) = 2. 5 v; refin(-) = 0 v; all specifications t min to t max , unless otherwise noted.) parameter ad7798/AD7799b unit test conditions/comments adc channel specification output update rate 4 hz min nom 500 hz max nom adc channel no missing codes 2 24 16 bits min bits min AD7799, f adc 125 hz ad7798 resolution 16 bits p-p gain = 128, 16.6 hz update rate 19 16 18.5 bits p-p bits p-p bits p-p gain = 1, 16.6 hz update rate, AD7799 gain = 1, 16.6 hz update rate, ad7798 gain = 64, 4 hz update rate, AD7799 output noise and update rates see tables in adc description integral nonlinearity 15 ppm of fs r max 3.5 ppm typ, gain 1 to 32 offset error 3 25 3 ppm of fsr max v typ gain = 64 or 128 offset error drift vs. temperature 4 10 nv/c typ full-scale error 5 10 v typ gain drift vs. temperature 4 0.5 ppm/c typ gain = 1, 2 3 ppm/c typ gain = 4 to 128 power supply rejection 90 db min 100 db typ, ain = 50 % of full scale analog inputs differential input voltage ranges refin/gain v no m refin = refin(+) C refin(C), gain = 1 to 128 absolute ain voltage limits 2 unbuffered mode buffered mode in-amp enabled gnd + 30 mv av dd C 30 mv gnd + 100 mv av dd C 100 mv gnd + 300 mv v dd C 1.2 v max v min v min v max v min v max gain = 1 or 2 gain = 1 or 2 gain = 4 to 128 common mode voltage in-amp enabled analog input current buffered mode or in-amp enabled 0.5 v min gain = 4 to 128 average input current 2 200 1 pa max na max ain1(+) C ain1(-), ain2(+) C ain2(-) only. ain3(+) C ain3(-). average input current drift 2 pa/c typ unbuffered mode average input current 400 na/v typ gain = 1 or 2 input current varies with input voltage. average input current drift normal mode rejection 2 @ 50 hz, 60 hz 50 70 pa/v/c typ db min 73 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 6 @ 50 hz 84 db min 90 db typ, 50 1 hz, fs[3:0] = 1001 6 @ 60 hz 90 db min 90 db typ, 60 1 hz, fs[3:0] = 1000 6 common mode rejection @dc @ 50 hz, 60 hz 2 90 100 db min db min ain = 50% of fs 80 db typ, fs[3:0] = 1010 6 50 1 hz (fs[3:0] = 1001 6 ), 60 1 hz (fs[3:0] = 1000 6 )
ad7798/AD7799 preliminary technical data rev. prd. page 4 of 17 parameter ad7798/AD7799b unit test conditions/comments reference input refin voltage 2.5 v nom refin = refin(+) C refin(C) reference voltage range 2 absolute refin voltage limits 2 0.1 av dd gnd C 30 mv v min v max v min av dd + 30 mv v max average reference input current 400 na/v typ average reference input current drift 0.03 na/v/c typ normal mode rejection 2 see analog inputs common mode rejection see analog inputs reference detect 0.3 0.65 v min v max noref bit inactive if vref < 0.3 v noref bit active if vref > 0.65 v low side power switch r on allowable current 5 7 20 ? max ? max ma max av dd = 5v av dd = 3v continuous current internal clock drift 64 2% 0.01 khz nom %/c typ logic inputs all inputs except sclk and din v inl , input low voltage 0.8 v max dv dd = 5 v 0.4 v max dv dd = 3 v v inh , input high voltage 2.0 v min dv dd = 3 v or 5 v sclk and din only (schmitt- triggered input) 2 v t (+) 1.4/2 v min/v max dv dd = 5 v v t (C) 0.8/1.4 v min/v max dv dd = 5 v v t (+) C v t (C) 0.3/0.85 v min/v max dv dd = 5 v v t (+) 0.9/2 v min/v max dv dd = 3 v v t (C) 0.4/1.1 v min/v max dv dd = 3 v v t (+) - v t (C) input currents input capacitance 0.3/0.85 1 10 v min/v max a max pf typ dv dd = 3 v v in = dv dd or gnd all digital inputs logic outputs v oh , output high voltage 2 dv dd C 0.6 v min dv dd = 3 v, i source = 100 a v ol , output low voltage 2 0.4 v max dv dd = 3 v, i sink = 100 a v oh , output high voltage 2 4 v min dv dd = 5 v, i source = 200 a v ol , output low voltage 2 0.4 v max dv dd = 5 v, i sink = 1.6 ma floating-state leakage current 1 a max floating-state output capa citance 10 pf typ data output coding offset binary digital outputs p1 and p2 v oh , output high voltage 2 v ol , output low voltage 2 v oh , output high voltage 2 v ol , output low voltage 2 av dd C 0.6 0.4 4 0.4 v min v max v min v max av dd = 3 v, i source = 100 a av dd = 3 v, i sink = 100 a av dd = 5 v, i source = 200 a av dd = 5 v, i sink = 800 a
preliminary technical data ad7798/AD7799 rev. prd. page 5 of 17 parameter ad7798/AD7799b unit test conditions/comments system calibration 2 full-scale calibration limit zero-scale calibration limit input span 1.05 x fs -1.05 x fs 0.8 x fs 2.1 x fs v max v min v min v max power requirements 7 power supply voltage v dd C gnd iov dd C gnd 2.7/5.25 2.7/5.25 v min/max v min/max power supply currents i dd current 150 a max 125 a typ, unbuffered mode 175 a max 150 a typ, buffered mode, in-amp bypassed 380 450 a max a max 330 a typ, in-amp used (ad7798) 400 a typ, in-amp used (AD7799) i dd (power-down mode) 1 a max 1 temperature range C40c to +105c. 2 specification is not production tested but is supported by characterization data at initial product release. 3 a system calibration will reduce this error to the order of the noise for the programmed gain and update rate. 4 a calibration at any temperat ure will remove this error. 5 full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (av dd = 4 v). 6 fs[3:0] are the four bits used in the mode register to select the output word rate. 7 digital inputs equal to dv dd or gnd.
ad7798/AD7799 preliminary technical data rev. prd. page 6 of 17 timing characteristics 8 , 9 table 2. (av dd = 2.7 v to 5.25 v; dv dd = 2.7 v to 5.25; gnd = 0 v, input logic 0 = 0 v, input logic 1 = dv dd , unless otherwise noted.) parameter limit at t min , t max (b version) unit conditions/comments t 3 100 ns min sclk high pulsewidth t 4 100 ns min sclk low pulsewidth read operation t 1 0 ns min cs falling edge to dout/ rdy active time 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 2 10 0 ns min sclk active ed ge to data valid delay 11 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 5 12 , 13 10 ns min bus relinquish time after cs inactive edge 80 ns max t 6 100 ns max sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high write operation t 8 0 ns min cs falling edge to sclk active edge setup time 11 t 9 30 ns min data valid to sclk edge setup time t 10 25 ns min data valid to sclk edge hold time t 11 0 ns min cs rising edge to sclk edge hold time 8 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 9 see and . figure 3 figure 4 10 these numbers are measured with the load circuit of figure 2 figure 2 and defined as the time required for the output to cross the v ol or v oh limits. 11 sclk active edge is falling edge of sclk. 12 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of . the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 13 rdy returns high after a read of the adc. in single conversion mode and continuous conversion mode, the same data can be read agai n, if required, while rdy is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. in continuous read mode, the digital word can be read only once.
prelim inary technical data ad7798/AD7799 r e v. prd . pa ge 7 o f 17 to o u tp u t p i n +1 . 6 v 50 pf f i g u re 2. l o ad c i rc uit f o r tim i ng ch ar ac te ri zat i on t 2 t 3 t 4 t 1 t 6 t 5 t 7 04227-0-003 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb f i gure 3. re ad c y c l e tim i ng d i ag r a m 04227-0-004 i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 f i gure 4. w r ite c y cl e tim i ng d i ag r a m
ad7798/AD7799 preliminary technical data rev. prd. page 8 of 17 absolute maximum ratings table 3. (t a = 25c, unless otherwise noted.) parameter rating av dd to gnd dv dd to gnd -0.3v to +7v -0.3v to +7v analog input voltage to gnd C0.3 v to av dd + 0.3 v reference input voltage to gnd C0.3 v to av dd + 0.3 v digital input voltage to gnd C0.3 v to dv dd + 0.3 v digital output voltage to gnd ain/digital input current C0.3 v to dv dd + 0.3 v 10 ma operating temperature range C40c to +105c storage temperature range C65c to +150c maximum junction temperature 150c tssop ja thermal impedance 97.9c/w jc thermal impedance 14c/w lead temperature, soldering vapor phase (60 sec) infrared 215c 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
prelim inary technical data ad7798/AD7799 r e v. prd . pa ge 9 o f 17 pin conf iguration and fu nction descriptions 3 4 5 14 13 12 dv dd av dd gn d 1 2 16 15 di n do u t / r dy 6 7 8 11 10 9 pwr s w ad 7 7 9 9 / 9 8 to p v i e w (n o t t o s c a l e ) re f i n( - ) re f i n( + ) ai n 3 ( + ) / p 1 ai n3 ( - ) / p 2 ai n 1 ( + ) sc l k cs ai n1 ( - ) ai n 2 ( + ) ai n2 ( - ) f i gure 5. pin configur ation ta ble 4. pi n f u nct i on des c ri pt i o ns pin no. mnemonic function 1 s c l k serial clock input for data tran sfer s to and from the adc. the sclk ha s a schmitt-triggered i n put, making the interface suitable for opto-i s olated app l icati o ns. the serial clock can be continuous with all d a ta transmitted in a continuous train of pulses. altern atively, it can be a nonc ontin u ous clock with the information bei n g transmitted to or from the adc in smaller batches of data. 2 cs chip select inpu t. this is an active low l o gic inpu t used to select the adc. cs can be used to select the adc in systems with more than one d evice on the se rial bus or a s a frame synchroniz ation signa l in c o mmuni- cating with the device. cs can be hard wired low, allo wing the adc to operate in 3-wire mod e wit h sclk, din, and dout used to interface with the device. 3 a i n 3 ( + ) / p 1 analog input/ digital output pin. ai n3(+) is the positive termin a l of the differential ana l og input pair ain3(+ )/ ain3 (-). al ternat ively, this pin c a n function as a gene ra l purpose output bit referenced between av dd and gnd 4 a i n 3 ( C ) / p 2 analog input/ digital output pin. ain3(C ) is the negative terminal of the differential ana l og in put pair ain3(+ )/ ain3 (-). al ternat ively, this pin c a n function as a gene ra l purpose output bit referenced between av dd and gnd 5 ain1(+) analog input. ain1 (+) is the positive terminal of the different ial analog input pair ain1(+ )/ ai n1(- ). 6 ain1(-) analog input. ain1(C) is th e negative terminal of the differential an alog input pair ain1(+ )/ ai n1(- ). 7 ain2(+) analog input. ain2 (+) is the positive terminal of the different ial analog input pair ain2(+ )/ ai n2(- ). 8 ain2(-) analog input. ain2(C) is th e negative terminal of the differential an alog input pair ain2(+ )/ ai n2(- ). 9 r e f i n ( + ) positive referen c e input. refin(+) can lie anywh e re between av dd and gnd + 0. 1 v. the nominal ref e rence vo ltage (refin(+) C refi n(C) ) is 2.5 v, bu t the part functi ons with a reference from 0.1 v to av dd . 10 refin(- ) negative reference input. this refe rence input can lie anywhere between gnd and av dd C 0.1 v. 11 psw low side power switch to gnd. 12 gnd ground reference point. 1 3 a v dd supply voltage, 2.7 v to 5.25 v. 1 4 d v dd serial interface supply voltage, 2.7 v to 5 v. dv dd is independent of av dd , therefore the seria l interface can be operated at 3v with v dd at 5v or vice versa. 15 dout/ rdy serial data output/ data ready output. dout/ rdy serves a dual pu rpose . it functions as a s e rial dat a output pin to access the output shift re gister of the ad c. the o utput sh ift register can contain data from any of the on-chi p data or control regi sters. in addition, dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not re ad after the conversi o n , the pin will go high before the next update occurs. the do ut/ rdy falling edge can be used as an interrupt to a pr ocess o r, indicating that val i d data is availabl e. with an external serial c l ock, th e data can be read using the do ut/ rdy pin. with cs low, the data/ c ontrol word informa-tion is placed on the dout/ rdy pin on the sclk falling edge an d is valid on the sclk rising edge. the end of a conversio n is also i n dicated by the rdy bit in the status register. when cs is high, the dout/ rdy pin is three-stated but th e rdy bit remains ac tive.
ad7798/AD7799 preliminary technical data rev. prd. page 10 of 17 pin no. mnemonic function 16 din serial data input to the inp ut shift register on the adc. data in this shift register is transferred to the control registers within the adc, the register selection bi ts of the communications register identifying the appropriate register.
prelim inary technical data ad7798/AD7799 r e v. prd . pa ge 11 o f 17 typical perf orm ance cha r acte ristics fi g u r e 6 . fi g u r e 7 . fi g u r e 8 . fi g u r e 9 . f i g u re 10. f i g u re 11.
ad7798/AD7799 preliminary technical data rev. prd. page 12 of 17 on-chip registers the adc is controlled and configured via a number of on-chip registers, which are described on the following pages. in the foll owing descriptions, set implies a logic 1 state and cleared implies a logic 0 state, unless otherwise stated. communications register (rs2, rs1, rs0 = 0, 0, 0) the communications register is an 8-bit write-only register. all communications to the part must start with a write operation t o the com- munications register. the data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. for read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. this is the d efault state of the interface and, on power-up or after a reset, the adc is in this default state waiting for a write operation to the communic ations regis- ter. in situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with din high ret urns the adc to this default state by resetting the entire part. table 5 outlines the bit designations for the communications register. cr0 thr ough cr7 indi- cate the bit location, cr denoting the bits are in the communications register. cr7 denotes the first bit of the data stream. t he number in brackets indicates the power-on/reset default status of that bit. cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen (0) r/ w (0) rs2(0) rs1(0) rs0(0) cread(0) 0(0) 0(0) table 5. communications register bit designations bit location bit name description cr7 wen write enable bit. a 0 must be written to this bit so that the write to the communications register actually occurs. if a 1 is the first bit written, the part will not cl ock on to subsequent bits in the register. it will stay at this bit location until a 0 is written to this bit. once a 0 is written to the wen bit, the next seven bits will be loaded to the communications register. cr6 r/ w a 0 in this bit location indicates that the next operation will be a write to a specified register. a 1 in this position indicates that the next operation will be a read from the designated register. cr5Ccr3 rs2Crs0 register address bits. these address bits are used to select which of the adcs registers are being selected during this serial interface communication. see table 6. cr2 cread continuous read of the data registe r. when this bit is set to 1 (and th e data register is selected), the serial interface is configured so that the data register can be continuo usly read, i.e., the contents of the data register are placed on the dout pin automati cally when the sclk pulses are applied. the commu- nications register does not have to be written to fo r data reads. to enable continuous read mode, the instruction 01011100 must be written to the communica tions register. to exit the continuous read mode, the instruction 01011000 must be written to the communications register while the rdy pin is low. while in continuous read mode , the adc monitors activity on the di n line so that it can receive the instruction to exit continuous read mode. additionally, a reset will occur if 32 consecutive 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is to be written to the device. cr1Ccr0 0 these bits must be programmed to logic 0 for correct operation. table 6. register selection rs2 rs1 rs0 register register size 0 0 0 communications register during a write operation 8-bit 0 0 0 status register during a read operation 8-bit 0 0 1 mode register 16-bit 0 1 0 configuration register 16-bit 0 1 1 data register 24-bit (AD7799) 16-bit (ad7798) 1 0 0 id register 8-bit 1 0 1 io register 8-bit 1 1 0 offset register 24-bit (AD7799) 16-bit (ad7798) 1 1 1 full-scale register 24-bit (AD7799) 16-bit (ad7798)
preliminary technical data ad7798/AD7799 rev. prd. page 13 of 17 status register (rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x88) the status register is an 8-bit read-only register. to access the adc status register, the user must write to the communication s register, select the next operation to be a read, and load bits rs2, rs1 and rs0 with 0. table 7 outlines the bit designations for the st atus register. sr0 through sr7 indicate the bit locations, sr denoting the bits are in the status register. sr7 denotes the first bit of the d ata stream. the number in brackets indicates the power-on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) noref(0) 0(0) 0/1 ch2(0) ch1(0) ch0(0) table 7. status register bit designations bit location bit name description sr7 rdy ready bit for adc. cleared when data is written to the adc data register. the rdy bit is set automatically after the adc data register has been read or a period of time before the data re gister is updated with a new conversion result to indicate to the user not to read the conversi on data. it is also set when the part is placed in power-down mode. the end of a conversion is indicated by the dout/ rdy pin also. this pin can be used as an alternative to the status register for monitori ng the adc for conversion data. sr6 err adc error bit. this bit is writte n to at the same time as the rdy bit. set to indicate that the result written to the adc data register has been clamped to al l 0s or all 1s. error sources include overrange, underrange, noref cleared by a write operation to start a conversion. sr5 noref no reference bit. set to indicate that one or both of the refin pins is floating or the applied voltage is below a specified threshold. when set , conversion results are clamped to all ones. cleared to indicate that a valid reference is applied between refin(+) and refin(-). the noref bit is enabled by setting the ref_det bit in the configuration register to 1. the err bit is also set if the voltage applied to the reference input is invalid. sr4 0 this bit is automatically cleared . sr3 0/1 this bit is automatically cleared on the ad7798, and is automatically set on the AD7799. sr2Csr0 ch2Cch0 these bits indicate which channel is being converted by the adc. mode register (rs2, rs1, rs0 = 0, 0, 1; power-on/reset = 0x000a) the mode register is a 16-bit register from which data can be read or to which data can be written. this register is used to co nfigure the low side power switch, select the mode of the adc and select the adc update rate. table 8 outlines the bit designations for th e mode register. mr0 through mr15 indicate the bit locations, mr denoting the bits are in the mode register. mr15 denotes the first bi t of the data stream. the number in brackets indicates the power-on/reset default status of that bit. any write to the setup register re sets the modulator and filter and sets the rdy bit. mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 md2(0) md1(0) md0(0) psw(0) 0(0) 0(0) 0(0) 0(0) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 (0) (0) 0(0) 0(0) fs3(1) fs2(0) fs1(1) fs0(0) table 8. mode register bit designations bit location bit name description mr15Cmr13 md2Cmd0 mode select bits. these bits select th e operational mode of the ad7798/AD7799 (see table 9). mr12 psw power switch control bit. set by user to close the power switch psw to gnd. the power switch can sink up to 20 ma. cleared by user to open the power switch. when the adc is placed in power-down mode, the power switch is opened. mr11-mr4 0 these bits must be programmed with a logic 0 for correct operation. mr3-mr0 fs3-fs0 filter update rate select bits (see table 10).
ad7798/AD7799 preliminary technical data rev. prd. page 14 of 17 table 9. operating modes md2 md1 md0 mode 0 0 0 continuous conversion mode (default). in continuous conversion mode, the adc continuously performs conversi ons and places the result in the data register. rdy goes low when a conversion is complete. the user can read these conversions by placing the device in continuous read mode whereby the conversi ons are automatically placed on the dout line when sclk pulses are applied. alternatively, the user can inst ruct the adc to output the conversion by writing to the communications register. after power-on, or follo wing a write to the mode, configuration or io registers, a conversion is available after a period 2/ f adc while subsequent conversions are available at a frequency of f adc . 0 0 1 single conversion mode. in single conversion mode, the adc is placed in power-down mode when conversions are not being performed. when single conversion mode is selected, the adc powers up and performs a single conversion, which occurs after a period 2/f adc . the conversion result in placed in the data register, rdy goes low, and the adc returns to power-down mode. the conversion remains in the data register and rdy remains active (low) until the data is read or another conversion is performed. 0 1 0 idle mode. in idle mode, the adc filter an modulator are held in a reset state although the modulator clocks are still provided 0 1 1 power-down mode. in power down mode, all the ad7798/99 circuitry is powered down including the power switch and burnout currents . 1 0 0 internal zero-scale calibration. an internal short is automa tically connected to the enabled channel. a calibration takes 2 conversion cycles to complete. rdy goes high when the calibration is initiated and returns low when the the calibration is complete. the adc is placed in idle mo de following a calibration. the measur ed offset coefficient is placed in the offset register of the selected channel. 1 0 1 internal full-scale calibration. the fullscale input is automatically connected to the selected analog input for this calibration. when the gain equals 1, a calibration takes 2 conversion cycles to complete. for higher gains, 4 conversion cycles are required for the fullscale calibration. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full-scale calibration coefficient is placed in the fullscale register of the selected channel. a fullscale calibration is required each time the gain of a channel is changed. the full-scale error of the AD7799/ad7798 is calibrated in the factory at both a gain of 1 and 128. these values are loaded into the fullscale register when the gain is 1 or 128. if a different pga gain is us ed, then an internal full-scale calibrat ion is required to calibrate out the gain error associated with that pga gain. note that in ternal fullscale calibrations cannot be performed at a gain of 128. 1 1 0 system offset calibration. user should connect the system zero-s cale input to the channel input pins as selected by the ch2-ch0 bits. a system offset calibration takes 2 conversion cycles to complete. rdy goes high when the calibration is initiated and returns low when the calibration is comp lete. the adc is placed in idle mode following a calibration. the measurded offset calibration coefficient is placed in the offset register of the selected channel. 1 1 1 system full-scale calibration. user should connect the system full-scale input to the channel input pins s selected by the ch2-ch0 bits. a system full-scale calibration takes 2 conversion cycles to complete. rdy goes high when the calibration is initiated and returns low when the calibration is comp lete. the adc is placed in idle mode following a calibration. the measured full-scale calibration coefficien t is placed in the fullscale register of the selected channel.
preliminary technical data ad7798/AD7799 rev. prd. page 15 of 17 table 10 . update rates available fs3 fs2 fs1 fs0 f adc (hz) tsettle (ms) rejection @50 hz/60 hz 0 0 0 0 x x 0 0 0 1 500 5 0 0 1 0 250 8 0 0 1 1 125 16 0 1 0 0 62.5 32 0 1 0 1 50 40 0 1 1 0 41.6 48 0 1 1 1 33.3 60 1 0 0 0 19.6 101 90 db (60 hz only) 1 0 0 1 16.6 120 84 db (50 hz only) 1 0 1 0 16.6 120 70 db (50 hz and 60 hz) 1 0 1 1 12.5 160 67 db (50 hz and 60 hz) 1 1 0 0 10 200 69 db (50 hz and 60 hz) 1 1 0 1 8.33 240 73 db (50 hz and 60 hz) 1 1 1 0 6.25 320 74 db (50 hz and 60 hz) 1 1 1 1 4.17 480 75 db @ 50/60 hz configuration register (rs2, rs1, rs0 = 0, 1, 0; power-on/reset = 0x0710) the configuration register is a 16-bit register from which data can be read or to which data can be written. this register is u sed to configure the adc for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the ana- log input channel. con0 through con15 indicate the bit locations, con denoting the bits are in the configuration register. con1 5 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. con15 con14 con13 con12 co n11 con10 con9 con8 0 0 bo(0) u/ b (0) 0(0) g2(1) g1(1) g0(1) con7 con6 con5 con4 con3 con2 con1 con0 0 0 ref_det(0) buf(1) 0(0) ch2(0) ch1(0) ch0(0) table 11. configuration register bit designations bit location bit name description con15Ccon14 0 these bits must be programmed with a logic 0 for correct operation. con13 bo burnout current enable bit. when this bit is set to 1 by the use r, the 100 na current sources in the signal path are enabled. when bo = 0, the bu rnout currents are disabled. the burnout currents can be enabled only when the buffer or in-amp is active. con12 u/ b unipolar/bipolar bit. set by user to enable unipolar coding, i.e., zero differential input will result in 0x0000(00) output and a full-scale differential input will result in 0xffff(ff) output for the ad7798(99). cleared by the user to enable bipolar coding. negative full-scale differential input will result in an output code of 0x0000(00), zero di fferential input will result in an output code of 0x8000(00), and a positive full-scale differential input will resu lt in an output code of 0xffff(ff) for the ad7798(99). con11 0 this bit must be programmed with a logic 0 for correct operation. con10-con8 g2-g0 gain select bits. written by the user to select the adc input range as follows g2 g1 g0 gain adc input range (2.5v reference) 0 0 0 1 (in-amp not used) 2.5 v 0 0 1 2 (in-amp not used) 1.25 v
ad7798/AD7799 preliminary technical information rev. prd. page 16 of 17 bit location bit name description 0 1 0 4 625 mv 0 1 1 8 312.5 mv 1 0 0 16 156.2 mv 1 0 1 32 78.125 mv 1 1 0 64 39.06 mv 1 1 1 128 19.53 mv con7-con6 0 these bits must be programmed to a logic 0 for correct operation. con5 ref_det enables the reference detect function. when set, the noref bit in the status register indi cates when the reference being used by the adc is not present. when cleared , the reference detect function is disabled. con4 buf configures the adc for buffered or unbuffered mode of operation. if cleared , the adc operates in unbuffered mode, lowering the power consumption of the device. if set , the adc operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. con3 0 this bits must be programmed to a logic 0 for correct operation. con2-con0 ch2-ch0 channel select bits. written by the user to select the ac tive analog input channel to the adc. ch2 ch1 ch0 channel calibration pair 0 0 0 ain1(+) C ain1(-) 0 0 0 1 ain2(+) C ain2(-) 1 0 1 0 ain3(+) C ain3(-) 2 0 1 1 ain1(-) C ain1(-) 0 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 vdd monitor data register (rs2, rs1, rs0 = 0, 1, 1; power-on/reset = 0x0000 (a d7798)/ 0x000000 (AD7799)) the conversion result from the adc is stored in this data register. this is a read-onl y register. on completion of a read opera tion from this register, the rdy bit/pin is set. id register (rs2, rs1, rs0 = 1, 0, 0; powe r-on/reset = 0xx8 (ad7798)/ 0xx9 (AD7799)) the identification number for the ad7798/AD7799 is stored in the id re gister. this is a read-only register. io register (rs2, rs1, rs0 = 1, 0, 1; power-on/reset = 0x00) the i/o register is an 8-bit register from which data can be read or to which data can be written. io0 through io7 indicate the bit locations, io denoting the bits are in the io register . table 12 outline the bit designations for the io register. io7 denotes the first bit of the data stream. the number in brackets indica tes the power-on/reset default status of that bit. io7 io6 io5 io4 io3 io2 io1 io0 0 ioen(0) io2dat(0) io1dat(0) 0 0 0 0 table 12. i/o register bit designations bit location bit name description io7 0 these bits must be programmed to a logic 0 for correct operation. io6 ioen configures the pins ain3 (+)/p1 and ain3(-)/p2 as analog input pins or digital output pins. when this bit is set , the pins are configured as digital output pins p1 and p2. when this bit is cleared , these pins are configured as anal og input pins ain3(+) and ain3(-). io5-io4 io2dat/io1dat p2/p1 data. io3-io0 0 these bits must be programm ed to a logic 0 for correct operation.
prelim inary technical information ad7798/AD7799 r e v. prd . pa ge 17 of 17 offset register (rs2, rs1, rs0 = 1 , 1, 0; powe r - on/reset = 0x8000 (ad7798)/0x80 0000 (AD7799)) the offset regist er holds t h e offs et cali br ation co efficient for the adc. the power-on-r es et v a lu e of the i n ter n al zero-scale c ali b ration coefficient regis t er is 8000 hex ( a d7798)/80000 0 hex (AD7799) . the ad7798 /AD7799 has 3 offset regist ers. each of these reg i ster s is a 16/24-bit read/write reg i ster. however, whe n writi n g to t h e o ffset-scal e regis t ers, the adc must be pl aced in power down mode or idle mode. t h is reg i ster is us ed in c o nju n ctio n wi th its assoc i at ed f u ll-scale register to form a re gis t er pair. the po wer-on-rese t v a lue is automatic a lly overwrit ten if a n int e rna l or sy stem zero-sc a le c a l i brat ion is i n it ia ted by the us er. fullscale register (rs 2 , rs1, rs0 = 1, 1, 1; power-on/reset = 0x5xxx (ad7798)/0x5xxx000 (AD7799)) the full-scal e register hol d s the full-scal e c a libratio n coefficient fo r the adc. the ad7798 /AD7799 has 3 ful l -scale reg i sters. each of thes e registers is a 16/24-bit read/wr i te reg i ster. however, whe n writ in g to th e full-scale reg i ste r s, the a d c mu st be pl aced in p o wer down mode or idle mode. the f u ll-scale error of the AD7799/ad7798 is cal i br ated in the facto r y at both a gain of 1 and 128. th erefore if the g a in is set to 128, as on power-on, or if the gain is set to 1, the factory cali brated internal f u ll-sc ale coeff i cients are au toma tically loaded into the full-scale reg i sters of th e ad779 9/ad7798. therefore, every device wi ll have different defaul t coefficients. th e user can overwrite t h es e values, if requir ed. the s e coeffi cients w i ll be au tomat i cal l y overwritte n if a n i n ternal or syste m full-scale c ali b ratio n is initiated by the user. a full-sc al e calibration s h ould be performe d when the g a in is changed. wh en the g a in equals 128, interna l full-sc ale calibr atio ns cannot be performed. ty pical a p plicati o n av dd in + in - ou t + ou t - r e f i n (-) gn d a v dd ad 77 99 / a d7 79 8 se r i a l in te r f a c e an d co n t r o l lo g i c si gm a d e l t a ad c ref e re n c e de t e c t in te r n a l cl o c k ain 1 ( + ) ai n1 ( - ) ain 2 ( + ) ain 2 ( - ) mu x in- a m p re f i n ( +) dou t / r d y din sc l k cs dv dd av dd gn d pw rs w f i g u re 12.

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